Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
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Realizing Low-Precision Storage and Sparse Execution in a Folded FPGA Speech Enhancer
Hardware-aware training often optimizes FPGA resources, latency, or bit operations, but folding changes what compression saves: shared arithmetic decouples precision, weight storage, and scheduled…Search-Guided Reasoning Trace Curation for Verilog Generation
Recent advances in large language models (LLMs) have improved Verilog generation.ChroNoC: A Tableless TDM Circuit-Switched NoC With Delay-Aware Deployment for Time-Sensitive Neuromorphic Computing
Time-sensitive neuromorphic architectures require predictable interconnects to preserve precise event timing.Combinatorial Lock for Trojan-Resilient AI Engines via Hash-Assisted Spectral Filtering
Multi-trigger backdoor attacks, in which heterogeneous trigger mechanisms (e.g., patch, blend, warping, and the latent-domain Spy-Watermark) coexist within a single poisoned model, cannot be…Optimizing Physical Neural Networks through Device Variable Selection
Physical neural networks (PNNs) leverage device physics in electronics, optics, and related domains to enable energy-efficient neural networks.Adapting DNNs to Embrace Voltage Scaling Induced Errors via Accumulation-Aware Quantization
The pervasive deployment of Deep Neural Networks (DNNs) across the computing spectrum has brought growing attention to energy efficiency, alongside raw performance.A Resource-Efficient and Precision-Scalable FPGA Accelerator for Spiking Neural Networks Using Minifloat Arithmetic
Spiking neural networks (SNNs) are well suited to event-driven edge intelligence, but the arithmetic complexity, memory footprint, and power consumption associated with conventional floating-point…Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
Functional verification of Register-Transfer Level(RTL) designs has become a critical bottleneck in modern semiconductor development, often consuming the majority of project resources.Decode Late, Multiply Once: Rethinking the Dot Product for Quantized Weights
Large neural networks are increasingly deployed with 1-4 bit weights and 16- or 32-bit activations, yet their dot products still use one multiplier per element.EGGPlacer: Energy-Guided Generative Chip Placement with Diffusion Models
Chip placement strongly affects routed wirelength and thermal behavior, yet these downstream metrics are difficult to evaluate during macro placement.TernScope: Model-Hardware Co-Design for Efficient Ternary Endoscopic Segmentation
Edge medical segmentation must reconcile small model size, high accuracy, and fast inference.FIGFLEX: A Mixed-Precision FP-INT GEMM Accelerator Co-Designed with Low-Bit LLM Quantization
Weight-only quantization keeps LLM activations in floating point and stores weights as low-bit integers, turning the dominant workload into floating-point-integer (FP-INT) general matrix…AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting
Analog circuit design still relies heavily on expert knowledge, and porting proven designs to new process nodes is a recurring bottleneck.Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey
Reinforcement learning (RL) enables adaptive and autonomous decision-making in embedded, edge, and heterogeneous computing systems.Learn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL Generation
Large-language-model register-transfer-level (RTL) generation has concentrated on how to train the model: fine-tuning, continued pre-training, and reinforcement learning from a verifier.Superposed analog memory for vector storage in neural networks
The growing memory demands of artificial neural networks pose a major challenge for energy-efficient computing, particularly for models that rely on large collections of high-dimensional weight and…A Generic On-Board AI Processing Chain for Earth Observation: From Application Development to Embedded Deployment and Mission-Level Orchestration
Earth observation satellites acquire more data than they can downlink.Injection of Space Radiation Errors on Low-power NVM using Generative Deep Learning
We develop an error model for a Non-Volatile Memory (NVM) device that represents the effects of physical faults experienced in a CubeSat mission in Low Earth Orbit (LEO).3D-MoE: Complementarity-Guided Hardware-Software Co-Design for MoE Decode on 3D-Stacked NMP
Mixture-of-Experts (MoE) have become a mainstream way to scale Large Language Models (LLMs), because each token activates only a small subset of experts, reducing inference cost.Sustainable Processing-in-DRAM Integration and Replacement for Transformer Inference Servers
Processing-in-DRAM (PID) accelerators are emerging as a sustainable alternative to GPUs for transformer model inference.