Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
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SMART-AIMC: Sensitivity-Aware Mixed ADC Resolution with Fine-Grained Tunability for Analog In-Memory Computing
Analog In-Memory Computing (IMC) is a promising paradigm for accelerating GEMM-based AI workloads by executing computations directly within the memory array in the analog domain.FieldRT: Reconfigurable Architecture from Geometric Sensitivity to Streaming Acceleration
Geometric perception on edge must simultaneously achieve two goals that are rarely addressed together: preserve accurate spatial understanding for object localization and operate within stringent…BitLLM: Efficient Low-Bit, Conversion-Hiding LLM Decoding on Mobile GPUs
The rapid scaling of large language models (LLMs) has unlocked remarkable capabilities across various domains.CAPER: Circuit-Aware Parameter-Efficient Reasoning in LLMs for Analog Verification
Large language models (LLMs) are increasingly used to generate analog circuits, yet every netlist must also be verified.TADA: Technology Aware DNN Accelerator Performance and Energy Estimator
Deep neural network (DNN) accelerators for edge inference must meet tight energy, latency, and area (EDP) constraints, and their optimal hardware architecture and dataflow configuration is typically…The Rise of Low Precision Floating Point
Floating point computing has dominated scientific computations since the 1950s because of its versatile ability to approximate real numbers with both sufficiently high precision and sufficiently…Tactus: Tactile & Pose Sensing Glove for Natural Dexterity Data Collection
Collecting naturalistic human manipulation demonstrations with accurate contact force and hand pose is essential for robot dexterous manipulation policy and foundational world model learning - yet…Learning to Formulate: Agentic Hardware-Software Co-Design of AI Infrastructure through Progressive Optimization and Verification
AI infrastructure, the chips and software that train and serve AI models, is designed in layers.OPERA: OPamp Design by an Expert-Taught Reasoning Agent, from Specifications to Layout
Analog flows from specifications to a signed-off layout rarely run without manual iteration.LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
Long-run RTL simulation of CPU candidates can take hours, while short diagnostic runs may miss performance degradation that emerges later in execution.How Far Are We From On-Device VLM Inference? A Measurement Study on Edge NPUs
Diverse optimizations spanning model architecture, inference runtime, and hardware acceleration have been proposed for on-device vision-language model (VLM) deployment on edge NPUs.FPGAFly: A 166.7k-Neuron Fruit-Fly Connectome on One FPGA via Deferred Spike Expansion and Shared-Codeword States
Synapse-resolution fruit-fly (Drosophila) connectomes enable neuron-by-neuron simulation of entire insect nervous systems, yet whole-brain models still require computationally demanding software or…A Case Study of a Multi-Agent Kernel-Optimization Loop That Learns a New AI Accelerator
Frontier large language models write correct CUDA kernels for most single-operator benchmark tasks, yet their accuracy collapses on accelerators whose architecture and programming language they have…The Code Behind the Layout: AI Agents for Analog Layout Generators
Analog layout remains largely manual and hard to automate.Streaming Speech Recognition on a Microcontroller: a 65.7M-Parameter Transducer in 2 and 4 Bits on the ESP32-P4
We run Kroko, a 65.7M-parameter streaming Zipformer2 transducer for English, on the ESP32-P4, a microcontroller with two 400 MHz RISC-V cores, a 128-bit SIMD extension (PIE) and 32 MB of PSRAM, but…Hardware-Matched Spiking Neural Networks for Real-Time Purkinje Cell Spike Classification
Distinguishing Purkinje cell (PC) simple spikes (SSs) from complex spikes (CSs) is key to studying cerebellar function.AnalogScout: Simulation-Efficient PVT-Aware Analog Sizing with LLM Agents
Analog device sizing must satisfy all specifications across process, voltage, and temperature (PVT) corners to ensure tape-out success, but simulating every candidate at all corners dominates the…Keeping Inference in the Radio: Design and Measurement of a Spiking Accelerator for mmWave ISAC Activity Recognition
Integrated sensing and communication allows wireless networks to recognize human activity from the channel estimates that the receiver computes anyway.SLICE-CiM: Selective Layer-wise Inference Control Engine with Confidence-Based Early Exit for SRAM based Digital Compute-in-Memory
Digital SRAM compute-in-memory (CIM) macros enable energy-efficient CNN inference by eliminating off-chip weight transfers; however, peripheral control logic introduces three inefficiencies: bit-…SPARTA: A Sparse Ternary LLM Accelerator with Adaptive Attention and Unified Datapath for Long-Context Edge Inference
LLMs on edge devices are constrained by limited memory and bandwidth.