Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
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Stop Paying by the Letter: Accelerating Full-Chip RTL Simulation with Host-Side Tokenized Logging
Firmware diagnostic logging (printf) is an essential debug instrument in full-chip SoC design verification, yet it imposes a heavy tax on cycle-accurate RTL simulation: formatting a 30-character…M3D-FLOW: A Monolithic 3-D-Stackable Processing-Near-DRAM Architecture for Generative Normalizing Flow Applications
Normalizing Flows (NFs) have shown strong results in generative modeling, recently reaching state-of-the-art image generation performance.Green Light: Carbon-Aware Design of Photonic Transformer Accelerators at the Edge
Migrating transformer inference to the edge requires sustainability considerations that encompass both operation and manufacturing, rather than operational energy alone.VHDLBench: Benchmarking and Fine-Tuning Large Language Models for VHDL-Based Chip Design
The rapid evolution of digital circuit complexity demands innovative approaches to hardware design automation.Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
Wiring and bandwidth bottlenecks between a quantum processor and room-temperature electronics can be reduced by placing digital control at the cryogenic stage, but commercial foundry standard-cell…SENTRY: A Streaming Edge Network Trust Engine for Real-Time Audio Deepfake Detection
Real-time voice cloning has enabled large-scale streaming deepfake and vishing attacks, while existing Network Detection and Response (NDR) solutions rely on GPU-based post-processing that requires…Replay Pruning and Few-Bit Integer Inference for Hardware-Efficient Speed-Sign Recognition
Speed-limit sign recognition on an automotive camera system-on-chip (SoC) must fit a detector and a classifier (the reader) into the memory, arithmetic, and energy budgets of the device.qGAMMA: A Framework for Optimal DNN Mapping on Multi-Precision Accelerators
This work describes qGAMMA, a flexible framework for exploring and optimizing the mapping of mixed-precision Deep Neural Network (DNN) models onto general-purpose spatial accelerators that support a…ConQUESTA: Topology-Aware Post-Training Structural Pruning of Quantum Neural Networks
Deploying quantum neural networks (QNNs) on sparse hardware requires preserving task accuracy while reducing compiler-induced two-qubit gates, SWAPs, and depth.HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs
High Bandwidth Flash (HBF) has recently emerged as a promising technology that provides terabyte-scale accelerator-local capacity at bandwidths approaching HBM, with a potential cost-per-bit…Client-Aware Security Adaptive Early Exit Vision Transformers for Heterogeneous Federated Learning
Federated learning (FL) trains a shared model across data-owning clients without centralizing raw data, but client data difficulty and compute budgets can differ.LoopHIL: Looping Hardware into LLM-assisted Agents for Wireless Embedded Systems
LLM agents are widely used for software development and debugging, but their adoption in embedded systems, especially for wireless tasks, remains limited.Who Plans, Who Edits? Verified, Cost-Aware Division of Labor for LLM-Driven Analog Layout Repair
Language-model agents can repair analog layouts when sign-off tools check every edit, but which model should plan a repair, which should edit it, and at what cost remain open questions.Where the SRAM Goes: Per-Symbol Attribution of Static Memory in FreeRTOS-C and Embassy-Rust IoT Firmware on a 64 KB RISC-V Microcontroller
Selecting a firmware stack for a memory-constrained microcontroller is usually guided by aggregate binary sizes, which report how much SRAM a build consumes but not where it goes or why.A Black-Box Positioning Solution for Effortless Integration in Wearable Navigation
Accurate localization is critical for a wide range of applications, including navigation, augmented reality, safety management, and healthcare.Independent Data-Integrity Verification for LLM-Driven Functional Coverage Closure in Hardware Design
LLM agents can write directed tests that close functional coverage, but coverage only shows that a state was reached, not that the data on the way there was correct.Compiling Multi-Threshold Operators for Quantized Non-Monotonic and Fine-Granular Activations in Custom-Tailored DNN Accelerators
Aggressive quantization of neural networks can expose activation functions as bottlenecks for efficient hardware acceleration.Architecting for Hardware Diversity: Meta's End-to-End Co-Design for High-Performance AI Training on AMD GPUs
Meta deploys a heterogeneous fleet comprising NVIDIA GPUs, AMD GPUs, and proprietary MTIA accelerators to reduce costs and mitigate vendor lock-in.X-RIC: An Agentic RAN-Intelligent Controller Benchmark for Enhancing Reinforcement Learning
The O-RAN ALLIANCE introduces architectural flexibility through disaggregation and AI-driven control.Understanding LLM Hallucinations Caused by Soft Errors
While hallucinations in Large Language Models (LLMs) have been extensively studied from a software perspective, limited attention has been paid to hardware-level factors.