Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
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Newest papers, page 5
ACE: An AI-Orchestrated Intrusion Detection and Compliance Mapping Engine
This study proposes the Automated Compliance Engine (ACE), an AI-orchestrated framework that links intrusion detection, regulatory control mapping, and automated countermeasure deployment for…HILO: Enabling Low-power, Dual-Band Communication using Tunnel Diode Oscillators
Wireless communication remains the most power-consuming operation in embedded systems.SafeDSE: Joint Exploration of Safety Architecture Patterns, Mapping, and Scheduling for Dataflow Applications With Safety Arguments (Extended Version)
Embedded platforms increasingly host safety-related streaming functions next to less critical ones.FORGE: Procedural Weight Generation for Sparse MoE Inference
We introduce FORGE (Fast On-chip Rotor Generation for Experts), a procedural weight generation system for Sparse Mixture-of-Experts (MoE) inference.LocalTrain: Integer-Only Local Learning for Energy-Efficient CNN Training on Edge FPGAs
Local learning reduces cross-layer training dependencies, but an efficient accelerator must still retain operands, accumulate gradients, and select quantization scales.When Is RTL Better? Auditing Evaluation Stability with Tool-Grounded Requirement Profiles
RTL-generation studies increasingly report functional correctness and post-synthesis quality, yet the evaluator itself is rarely treated as an experimental variable.Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure
Last-mile functional coverage closure for modern chip designs remains costly because a mature UVM environment exposes many controls while direct hits on the remaining bins are sparse.Stateless Stochastic Computing for Generative AI on Superconducting Logic: A Model-Hardware Co-Design
Thermodynamic computing lets stochastic physical dynamics carry out a computation and reads out the result as a time average.Heterogeneous Structured Pruning Under Resource Constraints for Hardware-Efficient Large Language Models
Training-free pruning removes weights from pretrained large language models to reduce their deployment cost.MoSAIC: Learning DAG Scheduling Heuristics from Optimal Schedules through Motif-Aware Recovery and LLM-Guided Reasoning
Efficient task scheduling in heterogeneous computing systems remains a fundamental challenge in embedded and high-level synthesis flows.A Hardware-Native Trapped-Ion Hybrid Qudit-Oscillator Instruction Set
Scaling trapped-ion processors by adding ions remains challenging.DynaTE: Accelerating Diffusion LLMs via Dynamic Token Execution
Diffusion-based LLMs (dLLMs) have recently emerged as a promising alternative to autoregressive (AR) LLMs by enabling bidirectional parallel refinement, alleviating the sequential decoding…Closed-loop evaluation of LLM agents for embedded software development
Large language models (LLMs) are increasingly deployed as coding agents that edit files, run builds and tests, inspect execution results, and repair software iteratively.DEX: Digit-Level Early Exit for Energy-Efficient MSDF Neural Network Inference
U-Net inference for brain-tumor segmentation requires billions of multiply-accumulate operations, motivating hardware that can reduce computation dynamically rather than relying only on fixed…AI-Driven, Timing-Aware Power Optimization
Post-route power recovery changes cell choices under tightly coupled timing, electrical and physical constraints, and the value of each change depends on what it costs to repair its side effects.When Algorithmic Exploration Becomes Cheap: A Case Study of Agentic Research in EDA
As EDA researchers, we conducted eight deliberate trials of agentic algorithm exploration, selecting several topics outside our areas of depth.Fault-tolerant foundation models
Emerging computer hardware often trades reliability for energy efficiency; here we show that large-language models (LLMs) can be trained to tolerate this unreliability, and that rather than…RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
Analog/RF circuits remain the critical interface between digital computation and the physical world, and emerging standards from Wi-Fi 7 to 6G place stringent demands on them, yet analog/RF design…The Missing Fourth Term for the Emulation Tensor Memory Equilibrium (TME) Model: The Residue Deconstruction Cost
The Tensor-Memory Equilibrium (TME) model of "FP8 is All You Need (Part 1)" calculates the execution time of Ozaki Scheme II emulation of fp64 as the maximum of a tensor-core term and a…CACHEFORGE: LLM-Guided End-to-End Generative Cache Replacement Policy for Performance and Hardware Efficiency
Modern cache replacement designs saturate because they operate within fixed representational structures, hand-crafted and heuristic based feature-engineered predictors, or offline imitation models…