Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
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Newest papers, page 6
A gem5-based Simulation Framework for Computing-in-DRAM
Computing-in-Memory using DRAM (CIMD) has demonstrated substantial energy and throughput gains for memory-bound workloads consisting of bulk-bitwise operations, by performing computation directly…ActTune: Action-Aware Precision and GPU Operating-Point Adaptation for Energy-Efficient Vision-Language-Action Inference
Vision-language-action (VLA) policies repeatedly invoke inference to control robots, making graphics processing unit (GPU) energy a recurring cost of task execution.X-OPM: Explainable Automatic Digital On-Chip Power Modeling for Enhanced Robustness
Proactive power management systems reduce processor dynamic power through runtime power prediction and power-aware scheduling.CXDVirt: Low Latency Kernel Module Based CXL-SSD Emulation
CXL-SSDs promise memory-semantic access to NAND-scale capacity through a small in-device DRAM cache, but scarce hardware makes emulation central to CXL-SSD research.A Survey on LLM-Integrated Hardware Design Verification
Large language models (LLMs) are increasingly being integrated into hardware verification to automate specification interpretation, verification-artifact generation, debugging, formal reasoning, and…6G NeXt - Towards 6G Split Computing Network Applications: Use Cases and Architecture
The definition of the sixth generation mobile communication is in the full swing.Co-Optimizing Graph Sparsification and Approximate Computing for Energy-Efficient FPGA-Based GCN Inference
Graph Convolutional Networks (GCNs) have emerged as a powerful framework for learning from graph-structured data, yet their deployment on resource-constrained edge platforms remains challenging due…Reinforcement Learning-Based Optimization of Workload-Aware Power Delivery Networks
Power Delivery Networks (PDNs) are critical components of modern VLSI chips, providing stable voltage levels while satisfying electromigration (EM) and IR-drop constraints.Evaluating Inference Compute for Generative AI: A Framework for Enterprise Workloads
LLM deployment is shifting from single-turn completion to agentic trajectories in which a model plans, calls tools, reads results and reasons at test time before acting.Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs
Modern edge Systems-on-Chip (SoCs) integrate heterogeneous processing units (PUs) such as CPUs, GPUs, and NPUs, each with distinct performance and energy characteristics.Deep Defence on Wheels: A Dual Intrusion Detection System Architecture for Comprehensive In-Vehicle Network Security
Increasing connectivity to the outside world and the lack of inbuilt security mechanisms have made legacy intra-vehicular networks vulnerable to cyberattacks.Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction
Integrated circuit design involves multiple design stages: logic synthesis, floorplanning, placement, and routing, with each stage taking hours to weeks to complete.Trinity: One Differentiable Physics for Training, Refining and Scoring Generative Floorplanners
Floorplanning arranges the blocks of a chip and decides their shapes under objectives that press blocks together, short wirelength and a small outline, and constraints that hold them apart…SparseCraft: Agentic Hardware-Software Co-Optimization for Sparse Computing
Sparse-accelerator design spaces are usually searched against analytical models, so a design point is admitted on what a model predicts rather than on what the hardware does.Beyond LLM Serving: Characterizing Vision-Language-Action Workloads for Embodied AI System Design
Vision-language-action (VLA) models translate multimodal observations into low-level robot actions.VHDL-REPOBENCH: A Repository-Level Benchmark for Evaluating Large Language Models on VHDL Design Generation
Large Language Models (LLMs) are increasingly applied in hardware design automation, demonstrating strong potential in generating and understanding hardware description languages.Cut Binary Cross Entropy: Efficient Large-Vocabulary Loss and Gradient Kernels for Sequential Recommendation
Industrial sequential recommender systems operate over massive item catalogs (e.g., 10^5--10^7 items).An Empirical Fault Vulnerability Exploration of ReRAM-based Process-in-Memory CNN Accelerators
Resistive random-access memory (ReRAM)-based Processing-in-Memory (PIM) accelerator is a promising platform for processing massively memory intensive matrix-vector multiplications of neural networks…JASPER: Special Session on Joint Reliability And Security Assessment of SPlit Computing for Edge Robustness
Split Computing (SC) enables efficient deployment of Deep Neural Networks (DNNs) by partitioning inference between edge devices and cloud servers.WakeKV: Reactive, Reversible KV Residency for Heads That Change Their Minds
Most KV-cache compression methods classify attention heads once, either offline or during prefill, and keep this classification fixed throughout generation.