Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
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Newest papers, page 9
Carry-Through Checksum: A Lightweight Fault-Detection for CNN Inference at the Edge
Convolutional Neural Networks (CNNs) are increasingly deployed in safety-critical edge applications, where soft errors can silently corrupt inference outputs and lead to unsafe decisions.OptiPrime: Optimizing Private Inference through Protocol-Hardware Co-design
Private deep neural network (DNN) inference based on hybrid homomorphic encryption (HE) and multi-party computation (MPC) can protect user data with a formal guarantee, but at the cost of…AI for Science with GPT-6 Astra: Thermal Design and Electrothermal Analysis of 2D CFET
Thermal optimization of 2D CFET inverters requires testing structural proposals against their electrical costs.FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
Approximate multipliers can reduce hardware area and energy consumption in Deep Neural Network (DNN) inference; however, they introduce computational errors.FairCompressAgent: An Agentic Framework for Fairness-Aware Model Compression for FPGA Deployment
Fairness-aware model compression requires selecting methods and configurations that balance accuracy, fairness, and deployment cost.CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning
Design verification remains one of the most resource-intensive stages of hardware development, often consuming up to 70% of the total design effort.A 25-$μ$s/inf Event-driven Graph Neural Network Processor with Spatiotemporal Caching and Spline Convolution for Ultra-low-latency AI at the Edge
Dynamic-vision-sensor (DVS) cameras generate events on a per-pixel basis with a $μ$s-level temporal resolution, calling for new algorithm-hardware co-design approaches compared to standard…LLM-enabled Behavior Driven Development Workflow for Formally Verified Hardware Designs
Recently, the use of Large Language Models (LLMs) for different tasks in the Electronic Design Automation (EDA) life-cycle has been studied extensively, but an integrated view is lacking.A Memristive Synapse for Online STDP Learning and Inference in SNNs
This work presents a fully analog memristive synaptic circuit for online spike-timing-dependent plasticity (STDP) learning in spiking neural networks (SNNs).Is INT8 Portable? A Cross-Platform Measurement Study of Quantized Inference on Embedded and Automotive Accelerators
Eight-bit integer (INT8) post-training quantization is the default recipe for edge deployment, under a widely held assumption: INT8 makes inference faster at a small, predictable accuracy cost, and…EBL: Efficient Broad Learning for Distributed Adaptive Harmonic Analysis
Renewable energy systems and electrified transport have found widespread adoption in recent years.Diagnosing Temporal Misalignment in Multichannel Time-Series Classification with Minimum Description Length
Multichannel time-series classification commonly assumes synchronized sensor streams, although latency, clock drift, and preprocessing can introduce relative delays during data collection or after…Hardware-Aware Learned Representation Compression for Distributed In-Sensor Vision
In-sensor computing reduces the cost of transmitting high-resolution image data by performing early-stage processing near the sensor.NeuroFlex: Lossless Element-Level ANN-SNN Co-Execution for Efficient Sparse Inference
Sparse DNN accelerators specialize in ANN or SNN execution, leaving energy or latency on the table when workload characteristics vary within a layer.Dissecting GPU Utilization for LLM Inference on Nvidia Hopper
A single SM utilization percentage can make an LLM inference workload look compute-saturated while hiding how much useful work is being done.BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inference
GPU memory bandwidth and capacity limit throughput in large language model (LLM) inference.Extreme-Scale Linear-Scaling Kohn-Sham DFT at 100 Million Atoms: Bridging Quantum Simulations and Experiments
Kohn-Sham density functional theory (DFT) remains the workhorse of ab initio materials simulation, yet cubic computational and quadratic memory scaling have confined calculations to a few hundred to…A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs
Artificial neural networks rely on vector-matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units.Efficient Vision-Language-Action Management and Serving for Robot Factories
Vision-Language-Action (VLA) models show high robotic manipulation capabilities via a two-stage design: a Vision-Language Model (VLM) stage followed by an Action Diffusion Transformer (ADiT) stage.Parallel Circuit Execution for Scalable Quantum Computation
Today's quantum processors have tens to hundreds of physical qubits, but reliable execution of arbitrary circuits remains limited to fewer than 30 entangled qubits across hardware modalities.