Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
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Newest papers, page 8
MicroQonv: Reshaping Convolution Tensors for Efficient Microscaling in Training and Inference
Microscaling quantization techniques are increasingly used to represent neural network parameters with 8 bits or fewer while preserving near-full precision accuracy.Accelerating the Mitigation of LLM Inference Nondeterminism Across GPU Architectures
Large language model (LLM) outputs are expected to be reproducible under greedy decoding, yet in practice the same model, prompt, and software stack produce different outputs on different GPUs.AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing
Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies.Bringing Chip Tapeout Into University Education
Providing students with experience from chip specification to fabricated silicon can strengthen chip-design education, but integrating tapeout into regular teaching is difficult to scale, especially…ScaleMPA: Rethinking Scalable RRT* Acceleration With a Grid-Native Representation
Real-time motion planning remains challenging in large and high-dimensional environments.NPU Accelerator: Quantized Real-Time Vehicle Detection on PYNQ-Z1 Using FINN
This paper presents the design, optimization, implementation, and on-board validation of a neural processing unit (NPU) accelerator for real-time vehicle detection on the resource-constrained Xilinx…SPECTRA: Adaptive Execution of Speculative Decoding on a Runtime-Reconfigurable Tiled Architecture
LLM inference on edge devices is constrained by computational and memory resources, making efficient autoregressive decoding challenging.Validation and Simulation Catch Different Errors: Four Levels of Evaluation for LLM-Generated Circuits
Simulation success is not equivalent to structural correctness for LLM-generated circuits.WaveletECO: A Closed-Loop Physical ECO Platform and a Specialized Local Language Model
Engineering change order (ECO) is an important step in repairing timing and electrical violations during the late stages of chip design.VSpector: Specification-Driven Bug Detection for RISC-V CPUs
Detecting RTL design bugs in open-source RISC-V CPU implementations is critical for ensuring system reliability.Bridging LLM Serving and CXL-SSDs with Chunk-Aware KV Cache Management
NAND-backed storage offers the capacity needed to scale LLM prefix caching, but its block I/O path incurs CPU cache contention and host-DRAM staging in addition to NAND latency.DVA-Neurons: Design and Verification of Adaptive LIF Neurons: From Single-Neuron Dynamics to Multi-Neuron Spiking Networks
Spiking Neural Networks (SNNs) offer a promising path toward ultra-low-power artificial intelligence inference by emulating the event-driven computation of biological neurons.Programming AMD XDNA NPUs with Open-source Compiler Tools: A FlashAttention Case Study
Spatial NPUs such as AMD XDNA place compute tiles beside small local memories and leave data movement between them to software.MiX: Micro-Inverted-Scaling for End-to-End Low-Bit Vision-Language Model Acceleration
The deployment of Vision-Language Models (VLMs) on edge devices is severely bottlenecked by memory bandwidth, necessitating aggressive sub-8-bit quantization.RISC-V and machine learning: a survey
The intersection of open-source processor architectures and machine learning is driving the demand for customizable, efficient, and accessible hardware.Can Agents Design Better Chips with a Higher Level Abstraction?
Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL.VeriBugBench: An Empirically Grounded Framework for Constructing Verilog RTL Debugging Benchmarks
RTL source-level debugging research requires benchmark artifacts that provide faulty designs together with precise change locations, executable test stimuli, and reproducible configurations.MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
Autoregressive transformer decoding is constrained by irregular key-value (KV) cache movement on tiled accelerators.Do AI Agents Understand Computer Architecture?
Agents are increasingly asked to design hardware, and increasingly reported to succeed.Decomposing Predictive Kubernetes Autoscaling for Large Language Model Serving Under Long Startup Delays
Large language model (LLM) inference deployed on Kubernetes faces an autoscaling challenge that conventional web services do not: new serving replicas take two to ten minutes to start because…