Systems & Networks · Computer Science & AI
Hardware Architecture
The newest papers in Hardware Architecture that ReadSearch has read, newest first. Each links to its own page, with its authors, date, where it was published and the original.
200 papers, from 31 August 2026 to 5 November 2026: 184 arXiv preprints and 16 OpenAlex records.
Get the few papers worth your time in Hardware Architecture every morning.
Follow Hardware Architecture and ReadSearch reads its new papers each day, then brings you the few worth reading, each with its key finding in a sentence.
Newest papers, page 10
HermiCache: Enclave-Aware Cache Replacement for Trusted Execution Environments
Trusted Execution Environments (TEEs) protect enclave memory from untrusted software but remain vulnerable to cache-based side-channel attacks due to shared microarchitectural resources.Routing Dense Layouts with History-Aware Offline Reinforcement Learning using LSTM
Detailed routing remains a dominant runtime bottleneck in physical design due to increasing complexity of design rules.DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity
Field-programmable gate arrays (FPGAs) enable efficient neural-network inference, but most deployment flows either accelerate multiply-accumulate operations or convert pretrained quantized models…TASTE: Throughput-Aware Batch Size Tuning for On-Device Edge Learning
The rise of privacy-preserving artificial intelligence (AI) has shifted the focus of model adaptation and personalization towards on-device learning, where deep learning models are finetuned…EStream: Fast and Memory-Efficient MoE Prefill through Expert Virtualization on Mobile NPUs
Mobile vendors and application developers increasingly deploy LLMs on smartphones for diverse prefill-only services.Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Accelerators
Multi-chiplet photonic neural network accelerators (MCPNAs) combine photonic computation, photonic communica-tion, and heterogeneous chiplet integration to enable scalable and energy-efficient AI…From Splats to Silicon: Rethinking Computational Efficiency of 3DGS
3D Gaussian splatting (3DGS) represents scenes with explicit primitives and supports real-time novel-view synthesis, yet its system efficiency varies substantially across scenes, viewpoints…Proton Irradiation Characterization of an Open-Source ML Accelerator on a Zynq UltraScale+ MPSoC
As spaceborne computing systems increasingly rely on neural network (NN) accelerators, the opacity of commercial, black-box architectures severely restricts the development of verifiable radiation…LLM-Driven Algorithm Design for Quantum Circuit Synthesis based on Binary Decision Diagrams
Quantum circuits are central to implementing quantum algorithms on quantum devices, where quantum gates must be reversible.RAGMark: A Comprehensive Framework for Benchmarking Retrieval-Augmented Generation Systems
We present RAGMark, a modular benchmarking framework for advanced Retrieval-Augmented Generation (RAG) systems targeting small-scale multi-GPU environments.Interface-Aware KV Cache Quantization for Dense On-Chip NVM in Long-Context LLM Decoding
The key-value (KV) cache is the dominant memory bottleneck in long-context large language model (LLM) decoding: every step reads it entirely, so decoding is memory-bandwidth bound.TreeFI: Value-Aware Statistical Fault Injection for Deep Neural Networks
Reliability evaluation of deep neural networks under hardware faults commonly relies on fault injection, but exhaustive campaigns are intractable for modern models and datasets.Cache-Aware Joint Router Adaptation for Memory-Efficient MoE Inference
Mixture-of-Experts (MoE) models activate few experts per token, yet their full expert sets can exceed GPU memory and require repeated weight transfers during decoding.JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability
Safety-critical real-time systems must satisfy multiple dependability requirements, notably time predictability and security.A Checklist to assess the energy and carbon impacts of ML/AI applications in Earth System Modeling
As machine learning and artificial intelligence find their way into nearly every aspect of climate, weather, and Earth system modeling, it is worth pausing to consider what our design decisions…Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems
Sharing analog integrated circuit designs remains difficult: foundry non-disclosure agreements restrict the process details a design depends on, and the testbenches behind published results are…Event-Driven Language Models with Sparse Neural Activity for Neuromorphic Hardware
Inference with transformer-based large language models (LLMs) is often limited by the memory-bound KV cache and quadratic attention cost.CHIPSMORE: Compute-in-Interconnect and -Memory Chiplets for Multi-Mode Multi-Request LLM Inference Acceleration
Large language model (LLM) inference exhibits substantial variability across adaptation modes, context lengths, and request concurrency, creating challenges for maintaining high utilization, memory…Clock-Gating Insertion Strategies on an Open-Source MSP430 Core: A Reproducible PPA Study and a Gate-Level Simulation Caveat
Clock gating, the standard technique for cutting dynamic power, is introduced either as hand-written behavioral clock gates at the register-transfer level (RTL) or as integrated clock-gating (ICG)…Developer Attitudes and Practices Towards Optimizing Software Energy Consumption
Software significantly influences the efficiency with which hardware resources are utilized, yet software energy consumption is seldom treated as a first-class concern in day-to-day development…